1. Field of the Invention
The present invention relates to a start-up circuit for starting a bias supply circuit and, more particularly, to an improvement in integration of a start-up circuit formed in a semiconductor integrated circuit.
2. Description of the Background Art
FIG. 10 is a circuit diagram of a conventional start-up circuit including a CMOS (complementary metal-oxide semiconductor). In FIG. 10, reference numeral 1 designates a power-supply potential point providing a power-supply potential V.sub.DD ; 2 designates a ground potential point providing a ground potential GND; reference character Q1 designates a P-channel MOS transistor having a source connected to the power-supply potential point 1; and R1 designates a resistor having a first end connected to the drain and gate of the P-channel MOS transistor Q1 and a second end connected to the ground potential point 2. A circuit enclosed by the dashed line indicated by reference numeral 3 is a start-up circuit. A bias supply circuit started by the start-up circuit 3 is enclosed by the dashed line indicated by reference numeral 4.
Reference character R2 designates a resistor having a first end connected to the power-supply potential point 1 and a second end connected to the bias supply circuit 4, and Q2 designates a P-channel MOS transistor having a source connected to the second end of the resistor R2 and a drain connected to the bias supply circuit 4. The P-channel MOS transistor Q2 whose gate is connected to the first end of the resistor R1 switches on/off in response to a voltage generated between the second end of the resistor R1 and the first end of the resistor R2.
The bias supply circuit 4 includes a resistor R3, PMOS transistors Q3, Q4, and NMOS transistors Q5 to Q7. Hereinafter, an N-channel MOS transistor is referred to as an NMOS, and a P-channel MOS transistor as a PMOS.
A first end of the resistor R3 and the source of the PMOS Q4 are connected to the second end of the resistor R2. The source of the PMOS Q3 is connected to a second end of the resistor R3, and the drain of the PMOS Q3 is connected to the drain of the NMOS Q5. The gate of the PMOS Q3 is connected to the gate and drain of the NMOS Q4. The drain of the NMOS Q6 is connected to the drain of the PMOS Q4, and the gate of the NMOS Q6 is connected to the gate and drain of the NMOS Q5. The sources of the NMOSs Q5, Q6 are connected to the ground potential point 2. The NMOS Q7 has a gate connected to the gate of the NMOS Q5, a source connected to the ground potential point 2, and a drain through which a DC current is supplied.
An exemplary design of the start-up circuit and bias supply circuit will be described below. It is assumed that the PMOSs Q1 to Q4, NMOSs Q5 to Q7, and resistors R1 to R3 are fabricated in the same process step. The size and characteristic values are as follows: the ratio of gate width to gate length (hereinafter referred to as W/L) of the PMOS Q1 is 200/3; the resistance of the resistor R1 is 150 k.OMEGA.; W/L of the PMOS Q2 is 30/3; the resistance of the resistor R2 is 5 k.OMEGA.; the resistance of the resistor R3 is 10 k.OMEGA.; W/L of the PMOS Q3 is 540/3; W/L of the PMOS Q4 is 40/3; and W/L of the NMOSs Q5 to Q7 is 10/2. The power-supply potential V.sub.DD is 5 V in normal operation.
FIG. 11 shows a layout of the start-up circuit 3 of FIG. 10 enlarged about 550 times. In FIG. 11, reference numeral 10 designates a gate electrode; 11 designates a source electrode; 12 designates a drain electrode; 13 designates a diffusion region; 14 designates a line for connection between respective electrodes, between an electrode and a diffusion region, or between diffusion regions; and 15 designates a contact hole for connection between the lines 14 and the electrodes or diffusion regions. Elements of FIG. 11 corresponding to those of FIG. 10 are designated by the same reference numerals and characters. The resistors R1 and R2 provide desired resistances by in-series connection of the plurality of diffusion regions 13 formed in the fabricating step of PMOS or NMOS transistors.
The operation of the start-up circuit 3 will be discussed below. The power-supply potential V.sub.DD is equal to the ground potential GND before the power supply is put to work. Thus a node 5 at the connection between the drain of the PMOS Q1 and the first end of the resistor R1 is at the ground potential GND when the power is applied.
The PMOS Q1, which operates in the same manner as a diode connected in the forward direction, begins to cause an ON-current to flow from the source toward the drain at the time when the power-supply potential V.sub.DD rising from the ground potential GND by the application of the power exceeds the threshold voltage of the PMOS Q1. This current flowing entirely to the ground potential GND through the resistor R1 generates a voltage across the resistor R1. Thus, the potential at the node 5 rises as the current increases or the power-supply potential V.sub.DD rises.
There is no current flow from the resistor R2 to the bias supply circuit 4 when the bias supply circuit 4 is not in operation, since the PMOS Q2 has the source connected to the power-supply potential point 1 through the resistor R2. Thus the source potential of the PMOS Q2 rises as the power-supply potential V.sub.DD rises. When the difference between the potential at the node 5 and the rising source potential of the PMOS Q2 exceeds the threshold voltage of the PMOS Q2, a drain current begins to flow.
If the gate potentials of the NMOSs Q5, Q6 of the bias supply circuit 4 rise as the PMOS Q2 turns on, the bias supply circuit 4 is started. As the bias supply circuit 4 is started, a current begins to flow through the resistor R2 to cause a voltage drop in the resistor R2. Then the source potential of the PMOS Q2 falls. As the potential at the node 5 rises, the PMOS Q2 turns off.
When the power-supply potential V.sub.DD falls instantaneously, for example, when the bias supply circuit 4 becomes inoperative, there is no current flow in the resistor R2 and the source potential of the PMOS Q2 becomes equal to the power-supply potential V.sub.DD. Then the gate-source voltage of the PMOS Q2 is higher than the threshold voltage of the PMOS Q2, and the drain current begins to flow in the PMOS Q2, whereby the bias supply circuit 4 is started.
FIG. 12 illustrates a bias supply circuit having a current supply direction different from that of the bias supply circuit of FIG. 10, and a start-up circuit corresponding thereto. In FIG. 12, reference character Q60 designates an NMOS transistor having a source connected to the ground potential point 2; R10 designates a diffused resistor having a first end connected to the power-supply potential point 1 and a second end connected to the drain and gate of the NMOS transistor Q60; R11 designates a diffused resistor having a first end connected to the ground potential point 2 and a second end connected to the bias supply circuit 4a; and Q61 designates an NMOS transistor having a gate connected to the second end of the resistor R10, a source connected to the second end of the resistor R11, and a drain connected to the bias supply circuit 4a.
The circuit enclosed by the dashed line indicated by reference character 3x is the start-up circuit. The bias supply circuit started by the start-up circuit 3x is enclosed by the dashed line indicated by the reference character 4a. The NMOS transistor Q61 switches on/off in response to a voltage generated between the second end of the resistor R10 and the second end of the resistor R11.
The bias supply circuit 4a includes a resistor R6, NMOS transistors Q19, Q20, and PMOS transistors Q21 to Q23. A first end of the resistor R6 and the source of the NMOS Q20 are connected to the second end of the resistor R11. The NMOS Q19 has a source connected to a second end of the resistor R6, a drain connected to the drain of the PMOS Q21, and a gate connected to the gate and drain of the PMOS Q20.
The PMOS Q22 has a drain connected to the drain of the NMOS Q20, and a gate connected to the gate and drain of the PMOS Q21. The sources of the PMOSs Q21 and Q22 are connected to the power-supply potential point 1. The PMOS Q23 has a gate connected to the gate of the PMOS Q21, a source connected to the power-supply potential point 1, and a drain through which a DC current is supplied.
In operation, as the potential at a node 18 rises up to not less than a threshold voltage V.sub.TH of the NMOS transistor Q60 immediately after the power supply is put to work, a drain current of the NMOS transistor Q60 flows through the diffused resistor R10. At this time, the potential at the node 18 is clamped at the threshold voltage V.sub.TH of the NMOS transistor Q60, and the current value equals (V.sub.CC -V.sub.TH) divided by the resistance of the diffused resistor R10. The source of the NMOS transistor Q61 is at the GND potential since there is no current flow in the diffused resistor R11. The NMOS transistor Q61 turns on since the potential at the node 18 is clamped at the threshold voltage V.sub.TH of the NMOS transistor Q60. Thus, the gate potentials of the PMOS transistors Q21 and Q22 fall, and a drain current of the PMOS transistor Q21 flows. This current causes a voltage drop in the diffused resistor R11, and the source potential of the NMOS transistor Q61 falls until the NMOS transistor Q61 turns off. Then the start-up circuit 3x turns off. The bias supply circuit 4a has already been stabilized in the ON-state, and thus the PMOS transistor Q23 operates as a constant current source.
The start-up circuit of FIG. 12, in which a voltage (V.sub.CC -V.sub.TH) is constantly applied across the diffused resistor R10, requires a high resistance of the diffused resistor R10 to reduce the current. The diffused resistor R11 also needs a high resistance, depending upon the constant current value of the supply circuit. This results in a very large layout area.
In the conventional start-up circuit as above described, the gate-source voltage V.sub.GS of the PMOS Q2 must be lower than the threshold voltage V.sub.TH thereof in order to turn off the PMOS Q2 in the steady state in which the bias supply circuit 4 is started. This necessitates a high potential at the node 5, resulting in a large pattern layout area for fabricating the resistor R1 simultaneously with the fabricating process of the PMOSs Q1 to Q4 and NMOSs Q5 to Q7.
Additional process of producing high resistances for reduction of the pattern layout area of the resistor R1 creates a need for more masks and more wafer process steps, resulting in increased fabricating costs.